Metal Oxide Semiconductor Field Effect Transistors

1. Overview

Metal-oxide-semiconductor-field effect transistors, or MOSFETs are made up of a MOS capacitor between two p-n diodes.

When no voltage is applied across the capacitor, current will not flow, since the circuit behaves like two p-n diodes in reverse bias.

When a negative voltage is applied across the capacitor, the negative charge on the contact attracts positive charge in the n-type silicon substrate to the boundary between silicon and insulator. These positive charges create a path for the positive charges being pushed from the p-doped source across the n-type substrate to the p-doped drain (ground). This is the fundamental idea behind MOSFET transistors.
The amount of current between source and drain is regulated by the gate voltage (capacitor voltage). With high voltage, a larger channel allows more current flow, as opposed to low voltage, which creates only a narrow channel that limits the current. The current flow can be determined from the following equation:

where k is the transductance parameter of the device; (Vg-Vt) is the voltage across the gate minus the threshold voltage; and (Vd+Vs) is the voltage drop across the source and drain.

2. Fabrication

The fabrication of MOSFETs involves four photolithography steps, three diffusion steps, and two vapor deposition steps. The procedure is as follows: (See page 5 for diagrams of procedure.)
Clean your chip in acetone for one minute and water for fifteen seconds; and etch in oxide etch for three minutes. The chip must be clean and pure for proper growth of the field oxide. Place the clean chip in the field oxide furnace for thirty minutes at 1100°C. The chip should have a purple color, representing the appropriate thickness of field oxide. (1) Clean chip with acetone and isopropanol, and spin on photoresist. Soft-bake the chip in an 85°C oven for twenty minutes. (2) Expose the photoresist with the boron diffusion mask in UV light for sixty seconds; then develop and rinse in water. Etch the chip in oxide etch for four minutes to remove field oxide in the exposed areas of the chip. (3) Ultrasonically clean the chip in acetone for one minute to remove the photoresist, and rinse in isopropanol. Place the chip in the boron diffusion furnace for thirty minutes at 950°C. The boron will diffuse into the silicon surfaces, but only a negligible amount will diffuse into the silicon dioxide regions. (4) Etch the chip in boron-glass etch for fifteen seconds, and water for fifteen seconds to remove excess boron. Clean the chip and apply photoresist in the same procedure as above. (5) Expose the photoresist with the gate oxide mask under UV light for sixty seconds, and develop. Etch the exposed field oxide in oxide etch for four minutes and rinse. (6) Remove the photoresist in acetone with the ultrasonic cleaner, and rinse in isopropanol. Place the chip in the gate oxide furnace for thirty minutes at 1000°C (1 ft3/hr), then switch to nitrogen for ten minutes (1 ft3/hr). (7) Clean the chip and apply photoresist. (8) Expose the photoresist with the aluminum contact mask under UV light for sixty seconds, and develop. (9) Etch the exposed oxide with oxide etch for four minutes and rinse. Evaporate aluminum onto the entire chip. (10) Remove the photoresist and excess aluminum with the lift off process ultrasonically clean the chip in acetone, and the aluminum on the photoresist will dissolve with the photoresist, leaving the aluminum only on the exposed areas. (11) Apply photoresist, expose with the aluminum mask, and develop. (12) Evaporate aluminum on both sides of the chip. (13) Remove photoresist and excess aluminum as in the above process. (14)

3. Results

During the fabrication process, I encountered three major difficulties: 1) The masks I used were too small for the equipment available to be precise in aligning the various mask patterns. Not only were the masks aligned imprecise, but the error resulting from the etching and diffusion processes was large compared to the size of my devices. 2) The concentration of the oxide etch was higher than expected, causing over-etch of the field oxide. This contributed to the difficulty I encountered in mask alignment, as the pattern on the chip was larger than the pattern on the mask. 3) The gate contact was too narow, which prevented a channel forming properly between the two diodes:

When I attempted to measure my devices, many of them behaved like diodes, which I attribute to current flowing from the gate to the drain, rather than from the source to the drain. The few devices I found that behaved as transistors did so on an extremely small scale, on the order of micro amps or nano amps. This can easily be explained by the narrow gate contact, which requires a large voltage to produce even a tiny current. The one "working" transistor I found had a rather unexpected and somewhat bizzare trait: as the gate voltage increased, the drain I-V curve decreased. I believe this can be explained the same way the diode behavior can be explained; that is, current was flowing from the gate to the drain, cancelling out the increased current from the source.
Another possible explanation for the non-ideal measurements I recorded may stem from the fact that my devices were so small. I found it rather difficult to get the test probes to contact my devices cleanly, since the area of the contacts was barely larger than the area of the probe leads. If, perhaps, a probe was not in full contact with the source, the only current across the device would be from the gate to the drain. If the gate probe contact was not clean, gate voltage increases would have little or no effect on the drain voltage (which might explain the graph reported above). If the there was a bad contact at the drain, no drain current would register at all.
Overall, I would say this lab went pretty well. Some things I need to remember for future labs are: 1) Monitor etching process to avoid overetching; 2) Remember that the mask printouts will be much smaller when transfered to the chip. Had I done these two things, I think my devices would have turned out better.