Tao Long

University of Illinois at Urbana-Champaign
Dept. of Electrical and Computer Engineering
As of March 19, 2000

URH #314 Sherman Hall
909 S. Fifth Street
Champaign, IL 61820
Phone: (217) 332-4686
E-mail: taolong@uiuc.edu
Homepage: http://www.ugcs.caltech.edu/~taolong


EDUCATION
Aug.1998 – Present	M.S., Electrical and Computer Engineering University of Illinois at Urbana-Champaign, Urbana-Champaign, Illinois Degree expected August, 2000 Overall GPA: 3.97; Major GPA: 3.97 (A = 4.0, A+ = 4.0)
	Related Coursework: VLSI System Design; Large Scale IC Design; Analog IC Design; Logic Design; VLSI in Signal Processing and Communications; Advanced Digital Signal Processing; Control System Theory and Design; Random Processes

Sept. 1994 – June 1998	B.S., Electrical Engineering California Institute of Technology (Caltech), Pasadena, California B.S. with Honor, June 1998 Overall GPA: 4.1; Major GPA: 4.1 (A = 4.0, A+ = 4.3)
	Related Coursework: CMOS VLSI Design; Solid-State Devices; Analog Circuit Analysis and Design; Circuit Theory; Transmission Lines; Communication-System Fundamentals; Digital Signal Processing; Analysis and Synthesis of Signals and Circuits; Microprocessor Systems; C/C++ Programming

WORK EXPERIENCE
July–Aug. 1998		Credence Systems Corporation; Fremont, California Hardware Engineer Intern, Kalos Project (memory IC tester) manufacturing group § Identified and debugged unstable circuits in DPS module due to joint problems in design and manufacturing steps.
June–Sept. 1997		Credence Systems Corporation; Fremont, California Hardware Engineer Intern, Kalos Project (memory IC tester) analog design group § Identified noise sources in the Level’s ASIC output on Kalos board. § Investigated approaches to reduce the noise in the Level’s ASIC output.
June–Sept. 1996		AstroTerra Corporation; San Diego, California Summer Intern § Improved the software and user interface for a multi-channel laser-beam phase-control board. § Designed an actuator control circuit for laser-communication equipment alignment.

RESEARCH AND TEACHING EXPERIENCE
Summer 1999		University of Illinois, Urbana-Champaign; Urbana-Champaign, Illinois VLSI and signal processing architecture course project development § Designed, simulated, synthesized and verified a digital RAKE receiver for a DS-CDMA wireless communication system. CAD tools included MATLAB, Synopsys, and Cadence.
Fall 1998		University of Illinois, Urbana-Champaign; Urbana-Champaign, Illinois Graduate Project of VLSI in Signal Processing and Communication Design § Developed a low-power high-throughput CDMA multiuser receiver architecture using adaptive gradient algorithm and dynamic algorithm transforms.
Fall 1996		California Institute of Technology (Caltech); Pasadena, California Undergraduate Project in VLSI Design § Designed, simulated and tested a synchronous CMOS IC that solves the Laplace-type partial differential equations in 2D. The chip consists of approximately 5,000 transistors, and was fabricated by MOSIS.

PUBLICATIONS
		§ T. Long and N.R.Shanbhag, ``Low-Power CDMA Multiuser Receiver Architectures,'' Signal Processing Systems (SiPS) Workshop, Taipei, Taiwan, Oct. 1999

Skills
		*CAD Tools:* Synopsys, Cadence, Mentor Graphics, Synopsis, Magic, HSPICE *Programming:* C/C++, Perl, Java, Intel 80x88 and Motorola 68HC Assembly *Hardware:* Debugging and troubleshooting complex analog and digital circuits

Awards And Honors
		§ Tau Beta Pi Scholarship (1998-99). § Caltech Carnation Merit Scholarship (1996-97 and 1997-98). § CESASC Scholarship, Chang Scholarship (1996-97 and 1997-98). § Member of Tau Beta Pi National Engineering Honor Society (since 1996).

REFERENCE	Available upon request.